Die or chip singulation is the separation of different dies (2) on a wafer (1) (see FIG. 1). It is the first of all assembly steps.
Die singulation by means of classical blade dicing is standard practice: dies are cut with a rotating wheel while a rinsing solution is spilled over the wafer in order to remove particles induced by the saw. This method requires dicing streets with a width of several tens of micron and gives rise to considerable sidewall damage (chipping, cracking). Especially when dicing through areas that contain metal dummies, which are present in copper damascene processing, the damage caused by ripping the metal pads out of the stack during dicing may be extensive.
Laser cutting is an alternative to classical blade dicing: here applying a laser beam onto it, evaporates material in the scribe lanes. This method is not subject to chipping; however, the heat generated by the laser beam may affect the properties of the material next to the dicing street. Hence an exclusion area where no circuitry is allowed is required near the dicing streets. Even without taking the heat-affected zone into account, the dicing streets achieved in this way are between 15 and 30 micron wide. No laser dicing solution exists that can cut through a stack with dummy metal pads in the scribe lanes.
Wafers or substrates are processed until completion of deposition, patterning and polishing of the last metal level below a passivation layer. A passivation layer is commonly known as a protective layer to assure the chemical stability of the layer(s) below. Both classical blade and laser dicing are performed after completion of the full wafer including passivation stack. Depending on the assembly route, a number of wafer level processes may be performed between passivation deposition and singulation (e.g. under bump metallization (UBM)/solder plating/redistribution layer deposition).
Trench etch dicing is a known technique, for instance from Advanced Packaging Materials, Processes, Properties and Interfaces, Proceedings of IEEE 01TH8562, ISBN 0-930815-64-5, pp. 92-97. Here, after completion of the wafer back end and the passivation stack, dicing streets are imaged and subsequently etched. This process gives rise to die edges that are very well defined (no chipping or cracking).
Trench etch dicing is capable of reducing considerably the scribe lane width required for dicing. In practice, the Si-gain is often limited by the fact that scribe lanes also contain electrical test structures and alignment features, which imposes a lower limit on the scribe lane width. Whereas blade dicing and laser dicing are performed scribe-by-scribe, trench etch dicing is a true wafer level process.
In all of the above mentioned processes, die singulation is performed after passivation. Hence, in all these processes, after singulation, only the top area of the die is passivated. Die edges are not protected.
In U.S. Pat. No. 5,925,924 methods for precise definition of IC chip edges are disclosed. Trenches are etched in the wafer to define the edges. Then the trenches are filled with an insulating material, which mechanically joins the IC chips of the wafer. It should be noted that an insulating layer is not always a passivation layer, which may be necessary for certain applications. Moreover the patent describes a method for stacking different dies or ICs, which are interconnected via the side surface of the resulting stack. Different etching steps are necessary to achieve this goal, since a discontinuous isolation layer on at least one side surface of the stack is required to allow the formation of interconnects.
Patent U.S. Pat. No. 5,597,766 relates to a method for detaching chips from an SOI substrate wafer, being a wafer covered by an insulating base layer. SiO2 layers are produced on the top surfaces of the dies and subsequently the complete die surface is covered with a passivation layer. Next trenches are etched between the chips down to the insulating layer of the substrate (i.e. the insulating layer serves as a stop layer for the trench etching) for separating the chips. Spacers are produced subsequently for passivation at the side-walls of the chips. Then wafer material is removed by etching from the backside in order to detach the chips.
Various aspects of the invention provide for a method for wafer dicing, which alleviates or avoids the problems of the prior art mentioned above.